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Signal Integrity Engineer at Infinera

Hello Dear Readers,   Infinera  has a vacancy for a Signal Integrity Engineer role. We are seeking a talented Signal Integrity Lead to join our dynamic team, contributing to the design and development of cutting-edge optical Products As an signal Integrity engineer focused on very high speed boards simulations, you will play a crucial role in designing and validating cutting-edge optical products. Key Responsibility: Signal Integrity, cross talk, Power Integrity planning Stack-up finalization Simulations, pre-post, and testing feedback Work closely with cross-functional teams Develop and implement methodologies for key re-suable designs Create detailed reports Qualifications: Bachelor's, Master's degree in Electronics, Electrical Engineering, or a related field. Must have simulated high-speed designs, including board-to-board and complex stack-up Strong problem-solving skills and the ability to troubleshoot complex SI problems Excellent communication Apply Here Connect with me 
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Analog Design Engineer at Texas Instruments

Hello Dear Readers, At Texas Instruments Bangalore, there is a vacancy for an Analog Design Engineer role. The Wide VIN Buck product line develops switching controllers for the >35V industrial, automotive and enterprise markets. The team in India is being expanded with a charter to own, drive and accelerate execution of product & technology road map in this Product line. The team will be set up with full product development ownership from definition till release to market. We are looking for analog designers with at least 1-2 yrs of industry experience in Analog design. This is a hands-on individual contributor role. Responsibilities include: Design function for projects - hands-on design of critical IP, own full chip top level, own sign-off for PG with layout and DV functions. Collaborate with the Test team pre- & post tape out, to achieve the best quality and lowest build cost. Collaborate with the Validation team pre- & post- tape out on coverage, and silicon debug.

ASIC Engineer, Architecture (University Grad) at Meta India

  Hello Dear Readers,   Meta India  has a vacancy for an ASIC Engineer, Architecture role. Meta Platforms Inc. is seeking an ASIC Engineer, Architecture to join our Infrastructure organization. This organization is responsible for building and maintaining the data centers that host all of our services - Facebook, Instagram, WhatsApp etc. These servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. In this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will be able to work with experts in video transcode, AI/ML and other technologies to evaluate algorithms, develop functional and performance models and help architect state-of-the-art hardware accelerator ASICs. Come work and learn alongside our expert engineers to build “Green” data center accelerators.  Responsibilities

Design Engineer I at Cadence Design Systems

Hello Dear Readers,   Cadence Design Systems  has a vacancy for Design Engineer I role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. Job Summary: We have an immediate opening in the System Validation team at Cadence Design Systems Bangalore, for the post of "Senior Design Engineer (IP System Validation)" (Grade “T1”). The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.