Case Sensitivity of VHDL        VHDL is not case sensitive . This means that the two statements have the exact same meaning (don’t worry about what the statement actually means though). Keep in mind that VHDL case-sensitivity and not good VHDL coding practices. if you write like the shown in below are an example.  Ex.  Dout <= A and B; ##Correct representation.         doUt <= a AnD b; ##Incorrect representation.    2. White Space in VHDL              VHDL is not sensitive to white space (spaces and tabs) in the source document. Once again, shown in below is not an example of good VHDL coding style.An example showing VHDL’s indifference to white space.  Ex.  nQ <= In_a or In_b;           nQ <=in_a   OR    in_b; 3. Comments in VHDL              it is always be...

VHDL has a rich and interesting history. But since knowing this history is probably not going to help you write better VHDL code, it will only be briefly mentioned here. Consulting other, lengthier texts or search engines will provide more information for those who are interested.  Regarding the  VHDL acronym,  the V is short for yet another acronym: VHSIC or Very High-Speed Integrated Circuit The HDL stands for Hardware Description Language Clearly, the state of technical affairs these days has done away with the need for nested acronyms. VHDL is a true computer language with the accompanying set of syntax and usage rules. But, as opposed to higher-level computer languages, VHDL is primarily used to describe hardware. The tendency for most people familiar with a higher-level computer language such as C or Java is to view VHDL as just another computer language. This is not altogether a bad approach if such a view facilitates the understanding and memoriz...

One of the longest standing “arguments” between engineers in digital design has been the issue of which is best—Verilog or VHDL? For many years this was partly a geographical divide, with North America seeming to be mainly using Verilog and Europe going more for VHDL, although this was not universal by any means. In many cases, the European academic the community was trending toward VHDL with its easy applicability to system level design and the perception that Verilog was really more a “low level” design language. With the advent of SystemVerilog and the proliferation of design tools, these boundaries and arguments have largely subsided, and most engineers realize that they can use IP blocks from either language in most of the design tools. Of course, individuals will always have their own preferences; however, it is true to say that now it is genuinely possible to be language agnostic and use whichever language and tools the user prefers. More often than not, the choice will depend...