VHDL Fundamentals Rules

1.  Case Sensitivity of VHDL

       VHDL is not case sensitive. This means that the two statements have the exact same meaning (don’t worry about what the statement actually means though). Keep in mind that VHDL case-sensitivity and not good VHDL coding practices. if you write like the shown in below are an example.

 Ex.  Dout <= A and B; ##Correct representation.

        doUt <= a AnD b; ##Incorrect representation.

   2. White Space in VHDL

            VHDL is not sensitive to white space (spaces and tabs) in the source document. Once again, shown in below is not an example of good VHDL coding style.An example showing VHDL’s indifference to white space.

 Ex.  nQ <= In_a or In_b; 

         nQ <=in_a   OR    in_b;

3. Comments in VHDL 

            it is always begin with the symbol “--” (two consecutive dashes). The VHDL synthesizer ignores anything after the two dashes. Unfortunately, there are no block-style comments (comments that span multiple lines but do not require comment marks on every line) available in VHDL.

Ex.

 -- This next section of code is used to blah-blah

 -- This type of comment is the best fake for block-style

PS_reg <= NS_reg; -- Assign next_state value to present_state

            Appropriate use of comments increases both the readability and the understandability of VHDL code normally it is required to explain the logic behind our design. The general rule is to comment any line or section of code that may not be clear to a reader of your code besides yourself. The only inappropriate use of a comment is to state something that is patently obvious. It is hard to imagine code that has too few comments so don’t be shy: use lots of comments. Research has shown that using lots of appropriate comments is actually a sign of high intelligence.keep in mind that you give appropriate comments while core logic is not delivered to third parties.  

4. VHDL Statements terminating

                  Similar to other algorithmic programming languages, every VHDL statement is terminated with a semicolon. This fact helps when attempting to remove compiling errors from your code since semicolons are often omitted during initial coding. The main challenge then is to know what constitutes a VHDL statement in order to know when to include semicolons. The VHDL synthesizer is not as forgiving as other languages when superfluous semicolons are placed in the source code.

 

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