One of the longest standing “arguments” between engineers in digital design has been the issue of which is best—Verilog or VHDL? For many years this was partly a geographical divide, with North America seeming to be mainly using Verilog and Europe going more for VHDL, although this was not universal by any means. In many cases, the European academic the community was trending toward VHDL with its easy applicability to system level design and the perception that Verilog was really more a “low level” design language. With the advent of SystemVerilog and the proliferation of design tools, these boundaries and arguments have largely subsided, and most engineers realize that they can use IP blocks from either language in most of the design tools. Of course, individuals will always have their own preferences; however, it is true to say that now it is genuinely possible to be language agnostic and use whichever language and tools the user prefers. More often than not, the choice will depend...