Case Sensitivity of VHDL VHDL is not case sensitive . This means that the two statements have the exact same meaning (don’t worry about what the statement actually means though). Keep in mind that VHDL case-sensitivity and not good VHDL coding practices. if you write like the shown in below are an example. Ex. Dout <= A and B; ##Correct representation. doUt <= a AnD b; ##Incorrect representation. 2. White Space in VHDL VHDL is not sensitive to white space (spaces and tabs) in the source document. Once again, shown in below is not an example of good VHDL coding style.An example showing VHDL’s indifference to white space. Ex. nQ <= In_a or In_b; nQ <=in_a OR in_b; 3. Comments in VHDL it is always be...