The substructure of CMOS including well mask, active region mask, poly mask and contact mask.

 Hello Dear Reader,

Credits of this complete article go to my classmates Jimmy Patel, Abhishek Pandya, Sony Dudhe, Nikul Panchal they have given us a very short summary of the substructure of the CMOS device.

 
CMOS Fabrication:

For less power dissipation requirement CMOS technology is used for implementing transistors. If we require a faster circuit then transistors are implemented over IC using BJT. Fabrication of CMOS transistors as IC’s can be done in three different methods.
The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively.
The Twin well technology, where NMOS and PMOS transistor is developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.
The silicon On the Insulator process, where rather than using silicon as the substrate an insulator material is used to improve speed and latch-up susceptibility.
 
N- well/ P- well Technology
CMOS can be obtained by integrating both NMOS and PMOS transistors over the same silicon wafer. In N–well technology an n-type well is diffused on a p-type substrate whereas in P- well it is vice- verse.
 
Making of CMOS using N well
Step 1: Manufacturing the n-well.
 
Step a: First we choose a substrate as a base for fabrication. For N- well, a P-type silicon substrate is selected.
Step b – Oxidation: The selective diffusion of n-type impurities is accomplished using SiO2 as a barrier which protects portions of the wafer against contamination of the substrate. SiO2 is laid out by the oxidation process done exposing the substrate to high-quality oxygen and hydrogen in oxidation the chamber at approximately 10000c
Step c – Growing of Photoresist: At this stage to permit the selective etching, the SiO2 layer is subjected to the photolithography process. In this process, the wafer is coated with a uniform film of a photosensitive emulsion.
Step d – Removal of Unexposed Photoresist: This step is the continuation of the photolithography process. In this step, a desired pattern of openness is made using a stencil. This stencil is used as a mask over the photoresist. The substrate is now exposed to UV rays the photoresist present under the exposed regions of the mask gets polymerized. The mask is removed and the unexposed region of photoresist is dissolved by developing wafer using a chemical such as Trichloroethylene.
Step e – Etching: The wafer is immersed in an etching solution of hydrofluoric acid, which removes the oxide from the areas through which dopants are to be diffused.
Step f – Removal of Whole Photoresist Layer: During the etching process, those portions of SiO2 which are protected by the photoresist layer are not affected. The photoresist mask is now stripped off with a chemical solvent (hot H2SO4).
Step g – Formation of N-well: The n-type impurities are diffused into the p-type substrate through the exposed region thus forming an N- well.
Step h – Removal of SiO2: The layer of SiO2 is now removed by using hydrofluoric acid.

Step 2: Manufacturing polysilicon and n-diffusion.

Step a – Deposition of Polysilicon: The misalignment of the gate of a CMOS transistor would lead to the unwanted capacitance which could harm the circuit. So to prevent this “Self-aligned gate process” is preferred where gate regions are formed before the formation of source and drain using ion implantation. Polysilicon is used for the formation of the gate because it can withstand the high temperature greater than 80000c when a wafer is subjected to annealing methods for the formation of source and drain. Polysilicon is deposited by using Chemical Deposition Process over a thin layer of the gate oxide. This thin gate oxide under the Polysilicon layer prevents further doping under the gate region.
Step b – Formation of Gate Region: Except for the two regions required for the formation of the gate for NMOS and PMOS transistors the remaining portion of Polysilicon is stripped off.
Step c – Oxidation Process: An oxidation layer is deposited over the wafer which acts as a shield for further diffusion and metallization processes.
Step d&e – Masking and Diffusion: For making regions for diffusion of n-type impurities using masking process small gaps are made.
Using diffusion process three n+ regions are developed for the formation of terminals of NMOS.
Step f – Removal of Oxide: The oxide layer is stripped off.

Step 3: Manufacturing p-diffusion, contacts, and metal.
 
Step a – P-type Diffusion: Similar to the n-type diffusion for forming the terminals of PMOS p-type diffusion is carried out.
Step b – Laying of Thick Field oxide: Before forming the metal terminals a thick field oxide is laid out to form a protective layer for the regions of the wafer where no terminals are required.
Step c – Metallization: This step is used for the formation of metal terminals which can provide interconnections. Aluminum is spread on the whole wafer.

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