Half Adder And Full Adder in All Level Of Abstraction Verilog Code

Hello Dear Reader,

Fig.1

Here given Fig.1 is one bit half adder in the lowest level of the abstration diagram is there as similarly we know their are two ways to designed one bit full adder either using two half adder and one or gate or designed using their separate boolean expression As shown in below Fig.2 and Fig.3.

Fig.2

   

Fig.3

Here in below section i have provided verilog code at all the levels of the digital system design such as Behavioural Level, Data or RTL Level, Structural Level.

Half-Adder:

1) Behavioural Level Verilog Code:

module half_adder(a,b,c,s
    );// behavioural model
input a,b;
output reg c,s;
always@(a,b)
begin
if((a&&~b)||(~a&&b))
s=1;
else
s=0;
if(a&&b)
c=1;
else
c=0;
end
endmodule

2) RTL or Data Flow Level Verilog Code:

module half_adder(a,b,c,s
    );// Dataflow level model
input a,b;
output c,s;
assign s=((a&&~b)||(~a&&b));
assign c=(a&&b);
endmodule

3) Structural Level Verilog Code: 

module half_adder(a,b,c,s
    );// Structural level model
input a,b;
output c,s;
wire w1,w2;
and g1(w1,~a,b);
and g2(w2,a,~b);
or g3(s,w1,w2);
and g4(c,a,b);
endmodule

RTL Viewer:

Fig.4

Simulational Result:

Full-Adder:

1) Behavioural Level Verilog Code:

module full_adder(a,b,cin,s,c
    );//behavioural level model
input a,b,cin;
output reg s,c;
always@(a,b,cin)
begin
s=a^b^cin;
c= (a&&b )||((a^b)&&cin);
end
endmodule

2) RTL or Data Flow Level Verilog Code:

module full_adder(a,b,cin,s,c
    );//Dataflow level model
input a,b,cin;
output s,c;
assign s=(a^b^cin);
assign c=((a&&b )||((a^b)&&cin));
endmodule

3) Structural Level Verilog Code: 

module full_adder(a,b,cin,s,c
    );//structural level model
input a,b,cin;
output s,c;
wire w1,w2,w3;
xor g1(w1,a,b);
and g2(w2,a,b);
and g3(w3,cin,w1);
xor g4(s,w1,cin);
or g5(c,w2,w3);
endmodule

4) Full Adder using Half Adder As Instance Model: 

module full_adder(a,b,cin,sum,carry);//structural level model
               input a,b,cin;
               output sum,carry;
               half_adder p1(a,b,c1,s);
               half_adder p2(s,cin,c2,sum);
               or g1(carry,c1,c2);
               endmodule

RTL Viewer:

Simulational Result:

Now Thank the reader for this post and I hope it might be helpful and give your suggestions in the comment box I will try to improve my side.

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