Hello Dear Readers,
Cadence Design Systems has a vacancy for Design Engineer I role.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
Job Summary:
We have an immediate opening in the System Validation team at Cadence Design Systems Bangalore, for the post of "Senior Design Engineer (IP System Validation)" (Grade “T1”).
The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.
- Pre Silicon emulation and Verification of System in NCSIM and Palladium.
- Hardware and Subsystem Design for all the Projects. (HW/SW infrastructure designed within team)
- Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet.
- Lead the Bringup, Debug, Compliance efforts and System level Characterization all the way to report release.
- Engage in interop and Customer Debug.
- Chance to work on cutting edge SERDES IP's from Cadence. Refer to Cadence Website for more details on our SERDES IP's.
- Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration.
- Hardware and Subsystem design expertise.
- The Kick in deploying and debugging your Solutions in different System environments.
Minimum Qualifications:
- 0-2 years (with Btech or Mtech) experience in Post-Silicon PHY and Systems Validation.
- Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES.
- Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
- Experience leading System validation efforts for SERDES solutions.
- Experience in PCIe LTSSM states is a plus.
- 0-2 years of experience in FPGA Design and Schematic design.
- 0-2 years of IP/SoC Physical Layer Electrical Validation experience.
- Familiarity with Verilog RTL coding, FPGA coding, python,C/C++
- Candidates are expected to be passionate about analog and digital electronic circuit design.
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