Hello Dear Reader, Fig.1 Here given Fig.1 is one bit half adder in the lowest level of the abstration diagram is there as similarly we know their are two ways to designed one bit full adder either using two half adder and one or gate or designed using their separate boolean expression As shown in below Fig.2 and Fig.3. Fig.2     Fig.3 Here in below section i have provided verilog code at all the levels of the digital system design such as Behavioural Level, Data or RTL Level, Structural Level. Half-Adder: 1) Behavioural Level Verilog Code: module half_adder(a,b,c,s     );// behavioural model input a,b; output reg c,s; always@(a,b) begin if((a&&~b)||(~a&&b)) s=1; else s=0; if(a&&b) c=1; else c=0; end endmodule 2) RTL or Data Flow Level Verilog Code: module half_adder(a,b,c,s     );// Dataflow level model input a,b; output c,s; assign s=((a&&~b)||(~a&&b)); assign c=(a&&b); endmodule 3) Structural Level Verilog

 Hello Dear Reader, Credits of this complete article go to my classmates Jimmy Patel, Abhishek Pandya, Sony Dudhe, Nikul Panchal they have given us a very short summary of the substructure of the CMOS device.   CMOS Fabrication: For less power dissipation requirement  CMOS technology  is used for implementing transistors. If we require a faster circuit then transistors are implemented over  IC using   BJT . Fabrication of  CMOS transistors  as IC’s can be done in three different methods. The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively. The  Twin well technology , where  NMOS  and PMOS transistor  is developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate. The silicon On the Insulator process, where rather than using silicon as the substrate an insulator material is used to improve speed and latch-up susceptibility.   N- well/ P- well T