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FGPA RTL Design Engineer at Tejas Networks

 Hello Dear Readers,

Currently at Tejas Networks vacancy for FGPA RTL Design Engineer role.

About the job:

Tejas Networks (A TATA COMPANY) are an R&D-driven organization founded in year 2000 in Bangalore, India. We are currently 750+ employees strong. We have offices in 10+ locations. Our products include carrier-grade optical transmission (based on DWDM/PTN/OTN/SONET-SDH technologies), fibre broadband (based on GPON/NG-PON), broadband wireless (based on LTE 4G/5G) as well as multi-gigabit Ethernet/IP switching and routing products

Our award-winning, feature-rich, cost-effective, reliable and flexible products are fully designed and manufactured in India and are used for building critical infrastructure across the globe. We are a true pioneer of the “Make in India” and “Atmanirbhar Bharat” initiative.

Location – Bangalore


Opportunities, roles, and responsibilities:

  • End-to-End FPGA ownership - Active involvement in design/architecture discussions, i/o assignment, documentation, coding, simulation, implementation, test-environment development (manual and automated), target-testing, debugging, release and support
  • Reading and comprehension FPGA/Processor/ASIC datasheets, user guides, technology standards and RFCs (ITUT, IEEE etc.)
  • Evaluation and proposal of FPGA device and associated memory components.
  • Adherence to the standard processes followed across the organization through the life cycle of the product
  • Interaction with hardware, software, diagnostics, firmware, product verification, customer support and quality audit teams.
  • Participation in end-to-end system design
  • Continuous learning, innovation and recognition

Skills we are looking for:

Technical skills:

  • Strong basics in digital design and communication networks.
  • Proficiency in HDL languages – Verilog/VHDL/System Verilog
  • Architectural knowledge and design experience with Xilinx/Intel/Lattice FPGAs is a must
  • Hands-on experience with High speed memories(QDR/RLDRAM/DDR3/DDR4), memory controllers, high-speed transceivers, and transceiver reconfiguration
  • A clear understanding of FPGA design elements like signal integrity, clock networks, clock-domain crossing, resource management, physical and timing constraints, static timing analysis, packet buffering, design closure techniques for area/timing/power, etc is highly preferred

 

Comments

  1. Anonymous6 October 2022 at 21:25

    Hello sir thanks for this post as I have shortlisted for this position and joined as R&D in FPGA position. Once again thanks for your guidance and your work.

    ReplyDelete
    Replies
    1. ELECTRONICS AND COMMUNICATION HUBS6 October 2022 at 22:02

      Great to hear you it's my pleasure and you can do same thing with others 👍👍🤗🤗

      Delete

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