Hello Dear Readers, Currently, at Intel  Bangalore vacancy for a Library QA Engineer role. Job Description: Validation of PDK libraries is the primary job. PDK libraries include primitive and analog device pcells/pycells. Validation by creating testcases and physical verification, extraction with multiple EDA tools Cadence/Synopsis/Siemens, Automating validation flows/testcase generation through Python, Skill and TCL are the primary responsibility. Following up on issues with development teams and interacting with multiple PDK stake holders etc is part of job. Qualifications: Candidate should have good knowledge about PDK, Pcells/Pycells, Front End and Back End custom design methodology with Cadence virtuoso/Synopsys Custom Design Platform.  Must have knowledge on synopsis, siemens, cadence physical verification flows and DRC/density error fixes. Candidate should be familiar with automation skills primarily - Skill, TCL and Python.  Good in written and verbal communi...

   Hello Dear Readers, Currently at Nvidia Bangalore vacancy for Design Engineer, PCIE role. NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world’s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can per...

  Hello Dear Readers, Currently, at Intel  Bangalore, Hyderabad vacancy for a Component Design Engineer role. Job Description: Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement. Required Skillset: This position involves developing and maintaining compact device models in internal and external circuit tools while working in a highly interactive team environment. Respo...

   Hello Dear Readers, Currently, at Silicon Labs   Hyderabad  vacancy for an  Applications engineer I - WiFi/BLE/Mesh role. Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.   About Silicon Labs: We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial...

  Hello Dear Readers, Currently, InnoPhase Bangalore has a vacancy for FPGA Design & Validation Engineer role. We are a leader in ultra-low-power wireless connectivity solutions for IoT products. Our award-winning Talaria TWO™ WiFi+BLE platform enables entirely new categories of smart devices using a unique, programmable digital polar radio architecture. We unleash the full potential of battery-based, direct-to-cloud, artificially intelligent, and machine-learning products such as smart door locks, remote security cameras, connected sensors, AR/VR, voice-activated A/V, wearables, and other energy-critical wireless IoT applications for a variety of markets. Our headquarters are in San Diego, California, with additional development centers in San Jose, CA, Kista, Sweden, and Bangalore, India. InnoPhase Bangalore is looking for a FPGA Design and Validation Engineer to join a growing start up  semiconductor development organization and to help drive excellence in our...

  Hello Dear Readers, Currently at Cadence Bangalore vacancy for a Product Engineer I role. Position Responsibilities: Support Cadence products in the Digital and Signoff team. Track and debug customer issues and work with R&D and release team on issue resolution. Run design benchmarks and develop flows and solutions. Position Requirements: MS/M.Tech in EE/ECE Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff. Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes. Exposure to, and solid understanding of, hierarchical design methodologies and low power design Energetic team player with a passion for problem solving Strong analysis skills with a track record to prove it Strong communication skills (verbal and written) Automation skills using Perl, Tcl and shell scripting Apply Here Conne...

Hello Dear Readers,   Currently at Seagate Pune  vacancy for Intern V- VLSI DI role. The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group in Pune participates in design, verification, physical design and  post-silicon validation activities of these complex SoCs. This group has some of the best talents from the industry and has taped out many controller chips. About the role - you will: Be able to work on block level Physical Design implementation using EDA tools for floor-planning, placement and timing analysis Understand Semicustom IC design flow using IP libraries, concepts of Verilog netlist, meaning of timing constraints and QOR checks Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing, timing analysis and equivalence checking for designs Work on Timing analysis for sign-off corners and modes, report generatio...