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Design Engineer I at Cadence Design System

 Hello Dear Readers,

Currently at Cadence Bangalore vacancy for a Design Engineer I role.

We have an immediate opening in the Post Silicon Physical Layer Electrical Validation team at Cadence Design Systems Bangalore, for the post of "Lead Design Engineer".

The responsibility entails performing pre-silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation primarily on Cadence's High Speed SERDES Test chips, ie,  activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.


What we are looking for in potential candidates is listed below:

  • 0-1 year (with Btech) or 0-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
  • Physical Layer electrical validation experience on AT LEAST ONE High-speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO, etc is MANDATORY
  • Hands-on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc is MANDATORY
  • Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing-related aspects.
  • 0-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping will be an added plus
  • Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug is an added plus.
  • Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, and TCL is an added plus

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