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ASIC/Layout Design Engineer at Synopsys

 Hello Dear Readers,

Currently, at Synopsys vacancy for ASIC/Layout Design Engineer role.

Job Description and Requirements:

You will be part of a rapidly growing development team in the area of GPIOs, Specialty IOs, and General Purpose Analog IPs

•You will develop layouts designs for Analog Full Custom IPs such as

  1. GPIOs , I2C, I3C , SMBUS , eMMC , SVID , Quad SPI , JTAG
  2. High-performance LVDS
  3. Crystal Oscillators
  4. Adaptive Bias Generator, Process Monitoring Block, Voltage Regulators
•You will be working with an experienced set of teams from various sites spread across the globe.


Technical Attributes:
•Good grip over CMOS circuit layout fundamentals, Technology effects, IO frame design methodology, Analog matching concepts
•Should have good understanding of layout and parasitic extraction.
•Should have good grip over automation /scripting languages


Personal Attributes:
•Has a dedicated desire to learn and explore new technologies.
•Demonstrates good analysis and problem-solving skills.
• High-energy person with the ability to go the extra mile.
•A proactive team player with good written and verbal communication skills.
•Networks with senior internal and external personnel in own area of understanding.


Apply Here

 

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