Hello Dear Readers,
Currently at NXP Semiconductors vacancy for Design Engineer - G2 role.
Job Opportunity:
Seeking highly motivated, energetic, team-oriented undergrad or postgrad students in the VLSI / Computer architecture domain, willing to go deeper into the logic design and take the challenge of developing Complex state-of-the-art IPs using the latest advanced Design flow methodologies and efficient techniques.
The person will be working closely with experienced and motivated team members of Systems, SoC / IP Design functions to address the design/architectural requirements in the context of the complex IP, Subsystem, and overall System level designs, providing a complete reusable solution with end to end design flow from High-level Specifications to actual design Implementation.
Key Responsibilities:
- Design and Develop complex IP and Subsystems across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.
- Member of IP / Subsystem team from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules.
- Ensure quality adherence during all stages of the IP development cycle and carry out a thorough implementation of existing processes, or build methodology to ensure ‘Zero Defect’ designs.
- Ability to work well as part of a team of global and local experts to influence and build technological innovations.
- Self starter with 3-5 years of experience in Verilog RTL Design concepts and develop complex IP design / Sub-system with minimal or no supervision.
- Good to have knowledge of Computer architecture, CPU design fundamentals, System architecture design for hardware IP / accelerators to be used in multiple domains like Vision and Radar processing, Device Peripherals, SoC Safety and Security functions etc.
- Strong fundamentals and concepts of multiple clocks in designs and various logic structures used for data / signal transfers across clock domains.
- Any exposure as part of course work, projects or work experience related to following domains is a big advantage
- Standard peripheral protocols and interfaces like PCIe, Ethernet, MIPI CSI/DSI, UFS, NOR Flash controllers
- Computer Vision and image processing functions.
- RISC-V CPU Architecture, general CPU fundamentals, DSP fundamentals
- Data Caches and architecture.
- Slow speed peripherals like SPI, CAN, LIN etc.
- Bus interfaces and standard protocols like AMBA AHB, AXI, APB and interconnect architecture.
- Functional Safety concepts specially related to Automotive but acceptable to have any other related safety standard exposure too.
- Exposure/experience of design tools and related methodologies like CDC, RDC, Static Timing, Synthesis and DFT is desirable though not mandatory.
- Strong fundamentals or hands on knowledge of HDLs (Verilog/VHDL) & Scripting languages (Perl, Tcl), C/C++ for hardware modeling.
- Understanding and having worked on FPGAs / Emulation board would be a significant added advantage as well.
Key Soft Skills:
- Good communication skills.
- Hands-on and ability to work well as part of a team both locally and with remote or multi-site teams.
- Fast Learner and proactive.
is it for fresher?
ReplyDeleteHa yes as they have written college graduate or post graduate but apply currently company doesn't looks into education they will mostly looking your projects list and some how your skills of different tools specific you have or not.
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